Vegasemi’s Design Verification (DV) Team have accumulated decades of solid ASIC verification know-how from working and partnering with many leading semiconductor companies.
SoC designs have become more sophisticated, integrating a wide range of IP including digital, Analog-Mixed Signal, embedded processors, memories, in-house and third-party IP into a single chip. This makes the chip verification a very challenging task requiring highly qualified verification engineers with advanced skills allowing them to work cross-functionally and execute tasks effectively with minimum resources to ensure cost-effective IC development. Our DV engineers have extensive experience driving complex Analog & Mixed Signal chip as well as an abundance of experience establishing verification methodology and driving the verification efforts of microarchitecture, especially ARM processor based SoC.
Our customers and partners can use our skilled Design Verification engineers to increase the size of their existing Design Verification teams or rely solely on our Team to execute verification. Our DV experts will architect a scalable verification environment (UVM) and the Verification plan, establish the verification methodology and select the verification techniques such as constrained-random or directed functional, formal, assertions along with self-checking to achieve the agreed upon coverage with no excess efforts. They will implement verification plan tests in the UVM environment using System-Verilog, System C/C and Assembler. They will also collaborate with analog designers on calibrated analog models using System Verilog or VAMS. They will determine the required level of modeling abstraction to achieve the verification objectives while maximizing runtime performance.
Our high quality Design Verification service and affordable cost allow our customers to accelerate the process of their IC Chip/SoC implementation by reducing the product development cycle and overall chip cost while meeting today’s aggressive deadlines and achieving a bug free-first silicon.
