"We cannot build the future of angstrom era system-on-chip (SoC) with methods created in the micron era."
— Ben Zaryouh, Founder & CEO, VegaSemi
About Us
Company
VegaSemi is a semiconductor technology company building runtime silicon intelligence for the next generation of AI-driven system-on-chip (SoC) platforms across edge and cloud computing. As AI workloads become more dynamic and compute-intensive, static design-time assumptions and coarse-grain control mechanisms are no longer sufficient to ensure efficiency, safety, security, reliability, or long-term correctness in modern silicon.
VegaSemi replaces fragmented, offline methodologies with a unified, fine-grain, real-time control architecture that continuously adapts power, performance, safety, and compute integrity in the field. This approach enables SoCs to operate efficiently and deterministically under changing workloads, environmental conditions, and silicon aging—without compromising performance or trust.
Purpose-built for the angstrom era, VegaSemi's technology delivers continuous correctness and scalable efficiency across both edge-intelligent systems and cloud-scale infrastructure.
Innovation
Technology
Modern compute-intensive system-on-chip (SoC) platforms demand more than incremental improvements. As silicon operates closer to physical limits and under increasingly dynamic AI workloads, traditional design-time assumptions and static or coarse-grain control mechanisms can no longer guarantee power efficiency, safety, security, reliability, or continuous correctness under real operating conditions.
VegaSemi introduces a new class of runtime SoC-level silicon intelligence. Our technology continuously observes and adapts system behavior in real time, enabling ultra-efficient power operation, resilient compute integrity, and continuous in-field assurance throughout the product lifetime.
By unifying power management, safety, security, reliability, and in-field validation within a single architectural framework, VegaSemi enables a fundamentally new way to design and operate trusted, high-performance silicon for the angstrom era.
Solutions
Products
Unified Architecture
VegaSemi products form a vertically integrated silicon control stack embedded within the SoC architecture and operating under a unified runtime control loop.
Rather than addressing power, safety, security, reliability, and test as isolated problems, VegaSemi technologies share a common foundation of real-time silicon sensing, telemetry, and closed-loop control.
This unified approach enables coordinated, workload-aware decisions across the entire SoC lifecycle — from performance and power optimization to functional safety, security resilience, aging management, and continuous in-field validation.
VegaPower™
Intelligent Runtime Power Control
VegaPower™ delivers ultra-fine-grain DVFS and power optimization by observing true silicon timing behavior in real time and operating within a continuous closed-loop control system. Unlike coarse-grain approaches—such as ring oscillators, replica paths, or speculative workload-inference techniques—VegaPower continuously senses actual functional timing stress, voltage droop, and in-situ silicon conditions, and feeds this silicon-truth telemetry back into the control loop to enable fast, accurate, and aging-aware power decisions across workloads and lifetime.
KEY IMPACTS:
Significant power and energy reduction by minimizing conservative voltage and frequency guardbands through continuous silicon-truth control
Ultra-low enablement overhead, avoiding large replica structures, heavy AI hardware, or intrusive instrumentation
Reduced SoC area and on-chip overhead, including lower reliance on large coupling capacitors and guardband-driven design margins
Simplified PMIC / IVR architecture, as fast transient events and droop conditions are handled locally in situ rather than externally
Simplified package and PDN design, enabled by relaxed decoupling, smoother transients, and reduced peak current stress
Lower thermal stress and improved reliability, resulting from workload-adaptive, fine-grain power regulation
Higher sustainable performance, achieved by safely operating closer to true silicon limits over lifetime
VegaSafe™ delivers runtime functional safety intelligence by continuously monitoring real silicon execution behavior under operational workloads and operating within a continuous runtime safety framework. Unlike traditional safety mechanisms based on static dual-core lockstep or offline in-field test, VegaSafe detects faults, timing anomalies, and divergence conditions as they occur in the field—enabling fast, coverage-rich, and common-cause-aware safety decisions across the SoC lifetime.
VegaSafe both enhances existing dual-core lockstep architectures and enables a safe single-core lockstep alternative. In dual-core configurations, VegaSafe mitigates fundamental safety limitations caused by common-cause failures, timing-correlated faults, and shared infrastructure dependencies. In single-core configurations, VegaSafe can meet or exceed the effective safety coverage of conventional dual-core lockstep while dramatically reducing area, power, memory, and system complexity—unlocking the use of large, high-performance XPUs in safety- and mission-critical systems.
VegaSafe is designed to support certifiable functional safety architectures aligned with automotive, industrial, avionics, aeronautics, and aerospace standards, including ISO 26262 (ASIL-D), IEC 61508, ISO 13849, DO-254, and DO-178C.
KEY IMPACTS:
Enhanced dual-core lockstep safety, mitigating common-cause and timing-correlated failure modes
Safe single-core lockstep, delivering dual-core-class safety coverage with significantly lower area and power overhead
Enables safety-critical deployment of large XPUs, without duplication-driven penalties or integration complexity
Runtime, scalable functional safety, aligned with automotive, industrial, avionics, and aerospace safety frameworks
VegaSecure™
Physical-Layer Runtime Silicon Security
VegaSecure™ delivers runtime silicon security intelligence by continuously monitoring real physical and micro-architectural execution behavior inside the SoC. Unlike traditional security mechanisms that rely primarily on protocol, firmware, or software enforcement, VegaSecure operates at the execution and physical layers, detecting abnormal behavior, timing anomalies, and malicious stress patterns as they occur within the hardware itself.
VegaSecure protects boot-critical and early execution phases of XPU operation against physical fault-injection attacks, including undervoltage manipulation, clock glitching, electromagnetic fault injection (EMFI), and laser fault injection (LFI). By observing execution integrity and timing behavior from the earliest stages of operation, VegaSecure detects and mitigates attacks that attempt to compromise secure boot, root-of-trust establishment, or early privilege transitions.
In addition to real-time detection and mitigation, VegaSecure generates rich physical-layer security telemetry, reporting attack occurrence, severity, and repetition to higher-level security software. This enables correlation, policy-driven response, and system-level mitigation within a broader defense-in-depth security architecture.
VegaSecure is designed to support certifiable and standards-aligned cybersecurity architectures across automotive, industrial, and mission-critical systems, including ISO/SAE 21434, UNECE R155, IEC 62443, and related aerospace, avionics, and critical-infrastructure security frameworks.
KEY IMPACTS:
Boot-phase and early-execution protection, detecting undervoltage, clock glitch, EMFI, and laser fault-injection attacks
Physical-layer security detection and mitigation, independent of software visibility
Rich runtime security telemetry, enabling attack occurrence, severity, and repetition analysis by security software
Execution-layer security awareness, extending protection beyond protocol- and software-only approaches
Standards-aligned cybersecurity enablement, supporting automotive, industrial, and mission-critical security frameworks
VegaTest™
Manufacturing & In-Field Test Intelligence — Unified
VegaTest™ delivers continuous silicon test and diagnostics across both manufacturing and in-field operation, enabling validation of silicon correctness throughout the entire product lifecycle. Unlike traditional approaches that treat production test and runtime validation as isolated phases, VegaTest provides a unified test framework that extends manufacturing-grade assurance into deployed systems without intrusive downtime or excessive test-data storage.
In manufacturing, VegaTest enables high-confidence at-speed validation while dramatically reducing test time. Tests that traditionally require seconds of execution on sophisticated ATE platforms—such as at-speed TDF/PDF, Vmin, and Fmax characterization—can be completed in milliseconds, significantly reducing test cost and dependency on complex tester infrastructure while improving manufacturing throughput.
By reducing reliance on pessimistic test assumptions and expanding observability under real operating conditions, VegaTest improves yield, correctness, and binning accuracy for complex SoCs. VegaTest also dramatically improves system-level test (SLT) effectiveness by providing meaningful validation in an environment where conventional SLT often lacks clear fault models.
KEY IMPACTS:
Orders-of-magnitude reduction in at-speed test time, shrinking TDF/PDF, Vmin, and Fmax tests from seconds to milliseconds
Lower manufacturing test cost, reducing dependency on long ATE execution and complex tester configurations
Improved yield and binning accuracy, enabling better separation of marginal and high-quality silicon
Higher confidence SoC correctness, beyond what is achievable with factory-only test
Dramatically enhanced SLT effectiveness, addressing the lack of clear fault models in traditional SLT
Unified manufacturing and in-field test, enabling lifecycle-wide silicon assurance with minimal overhead
VegaTest further accelerates manufacturing by enabling true at-speed functional validation that traditionally requires several seconds of execution on advanced ATE platforms. Such long execution times make at-speed tests—including TDF/PDF, Vmin, and Fmax characterization—a dominant contributor to manufacturing cost and often force compromises in test coverage.
By reducing test duration from seconds to milliseconds, VegaTest fundamentally changes the economics of at-speed testing. This dramatic reduction in test time significantly lowers manufacturing cost, improves tester throughput, and enables more effective screening of timing- and voltage-sensitive defects without increasing reliance on complex ATE configurations.
This capability directly improves yield, binning accuracy, and overall SoC correctness, enabling better separation of marginal and high-quality silicon. By replacing pessimistic assumptions with faster, more representative validation, VegaTest strengthens confidence in production screening results.
VegaTest also dramatically enhances system-level test (SLT) by introducing meaningful fault observability in an environment where conventional SLT often lacks clear and actionable fault models. This transforms SLT from a coarse screening step into a higher-value validation phase that better correlates manufacturing results with real operational behavior.
Standards alignment:
Manufacturing, quality & test standards
ISO 26262 (Automotive Functional Safety)
Supports production test, diagnostic coverage, and in-field confidence
Improves confidence in latent fault detection and timing-related failures
Strengthens ASIL-B → ASIL-D safety-case arguments by reducing uncertainty in test effectiveness
AEC-Q100 (Automotive IC Qualification)
Accelerates at-speed screening and exposure of marginal silicon behavior
Improves detection of timing-, voltage-, and stress-sensitive defects
Supports lifetime reliability confidence by maintaining continuity from manufacturing to operation
JEDEC (Reliability & qualification guidelines)
Complements JEDEC stress and characterization with runtime validation
Improves correlation between factory screening and field behavior
Industrial & mission-critical standards
IEC 61508 (Functional Safety – Industrial)
Aligns with diagnostic coverage, proof-test concepts, and online diagnostics
Strengthens continuous test arguments versus periodic shutdown-based testing
ISO 13849 (Industrial Machinery Safety)
Improves diagnostic coverage (DC) metrics and runtime confidence
Enables validation without stopping machines or introducing intrusive downtime
Aerospace / avionics / high-reliability
DO-254 (Avionics Hardware)
Supports manufacturing assurance, fault detection, and in-service monitoring arguments
Strengthens design assurance evidence with runtime correctness visibility
DO-178C (System-level context)
Reinforces hardware correctness assumptions used by software safety cases
Transforms SLT from a coarse screening step into a higher-value validation phase
ISO 9001 / IATF 16949 (Quality Management)
Improves process capability, yield predictability, and traceability
Reduces escape risk and field returns through stronger screening and validation continuity
Updates
News
January 2026
VegaPower™ — Runtime Power Intelligence for Modern SoCs
As compute-intensive SoCs operate closer to physical limits, power management and power integrity can no longer rely on static margins or coarse-grain control. Real workloads, fast transients, environmental variation, and silicon aging demand a fundamentally different approach.
VegaPower technology enables ultra-fine-grain dynamic voltage and frequency scaling (DVFS) tightly coupled with real-time power integrity intelligence, forming a unified runtime power management framework at the silicon level.
By continuously observing workload behavior and supply conditions in the field, VegaPower enables SoCs to operate at optimal efficiency while maintaining stable, reliable power delivery under all operating conditions.
Designed for AI-centric edge and cloud SoCs, VegaPower enables substantial power efficiency gains without compromising performance, robustness, or long-term correctness.
VegaPower is the first realization of VegaSemi's unified runtime silicon intelligence architecture—purpose-built for the angstrom era of power-constrained, compute-intensive systems.
VegaSemi welcomes discussions for collaboration, evaluation, and licensing of VegaPower technology.
We invite SoC designers, platform integrators, and ecosystem partners to explore next-generation power management and power integrity solutions.
